The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
As one of semiconductor devices, there is DRAM (Dynamic Random Access Memory) that includes a memory cell section which contains word lines and bit lines, and a peripheral circuit section which is arranged around the memory cell section and drives memory cells of the memory cell section.
In order to respond to demands for miniaturization, the DRAM employs a structure in which the word lines that select the memory cells are embedded in a semiconductor substrate and the bit lines are formed on the semiconductor substrate (For example, see Japanese Patent Application Laid-open No. 2011-129771).
Japanese Patent Application Laid-open No. 2011-129771 discloses a method of forming at once gate electrodes of planar transistors in a peripheral circuit region along with bit lines when the bit lines are formed in a memory cell region.
More specifically, first, a laminated film is formed as a high-concentration n-type impurity implantation polysilicon film, a metal film and a silicon nitride film are laminated on both the memory cell region and the peripheral circuit region.
The high-concentration n-type impurity implantation polysilicon film and metal film formed on the memory cell region are conductive films that are used as base material of the bit lines. The high-concentration n-type impurity implantation polysilicon film and metal film formed on the peripheral circuit region are conductive films that are used as base material of the gate electrodes of planar transistors, which are disposed in the peripheral circuit region.
After that, the photolithographic and dry-etching techniques are used to perform patterning of the laminated film. As a result, the bit lines that are disposed on the memory cell region, and the gate electrodes of the planar transistors that are disposed on the peripheral circuit region are formed at once.
In the case of Japanese Patent Application Laid-open No. 2011-129771, the bit lines and the gate electrodes of the planar transistors disposed in the peripheral circuit region employ a poly-metal gate structure.
The poly-metal gate structure is made up of a polysilicon film and a metal film, which is laminated on the polysilicon film.
FIG. 15 is a cross-sectional view illustrating a process of manufacturing a structure (or a structure containing bit lines) that is disposed on the memory cell region. FIG. 15 is an enlarged cross-sectional view of a portion in which a bit line contact plug 306 and a bit line 321 are placed, in a memory cell section 300 that is disposed in the memory cell region.
FIG. 16 is across-sectional view illustrating a process of manufacturing a structure (or a structure containing gate electrodes of planar transistors) that is disposed on the peripheral circuit region. FIG. 16 is an enlarged cross-sectional view of a region in which a gate electrode 335 of a planar transistor is placed, in a peripheral circuit section 330 that is disposed in the peripheral circuit region. In FIG. 16, the same components as those of the memory cell section 300 shown in FIG. 15 are represented by the same reference symbols.
With reference to FIG. 15, a method of manufacturing the memory cell section 300 disposed in the memory cell region will be described.
First, the well-known photolithographic and dry-etching techniques are used to form a bit contact hole 304A: the bit contact hole 304A passes through a bit-contact interlayer insulation film 304, which covers an upper surface of an active region 301 and an upper surface of an element isolation region 302 defining the active region 301 (cell active region), and the bit contact hole 304A exposes the upper surface of the active region 301.
Then, a well-known technique is used to fill the bit contact hole 304A with polysilicon film. As a result, what is formed is a bit line contact plug 306 that is made of the polysilicon film and whose lower end is in contact with the upper surface of the active region 301.
Then, a well-known technique is used to sequentially laminate a Poly-Si film 308, which covers an upper end surface of the bit line contact plug 306 and an upper surface of the bit-contact interlayer insulation film 304, a metal laminated film 309, and a silicon nitride film 312.
The metal laminated film 309 is formed by sequentially laminating a TiSi film 314, a TiN film 315, a WSi film 316, and a W film 317.
Then, a well-known technique is used to perform patterning of the silicon nitride film 312. As a result, what is formed is a cap insulation film 319 that is made of the silicon nitride film 312 and which covers an upper surface of the W film 317 corresponding to a formation region of the bit line 321.
Then, the cap insulation film 319 is used as an etching mask, and patterning of the Poly-Si film 308 and the metal laminated film 309 by anisotropic dry etching is performed. As a result, what is formed is the bit line 321 that is made up of the Poly-Si film 308 and the metal laminated film 309.
Then, a well-known technique is used to form a sidewall 323 that covers a side surface of the bit line 321 and a side surface of the cap insulation film 319.
Then, a well-known technique is used to form a capacitance-contact interlayer insulation film 325, which fills the space formed between adjacent sidewalls 323. In this manner, the memory cell section 300 is produced.
With reference to FIG. 16, a method of manufacturing the peripheral circuit section 330 disposed in the peripheral circuit region will be described.
First, a well-known technique is used to form a gate insulation film 333 on an active region 331 (or an active region where a peripheral-circuit transistor is formed) that is located in the peripheral circuit region.
Then, on an upper surface of the gate insulation film 333, a step-reduction Poly-Si film 334, a Poly-Si film 308, a metal laminated film 309, and a silicon nitride film 312 are sequentially laminated.
Incidentally, the Poly-Si film 308, the metal laminated film 309, and the silicon nitride film 312 are formed at the same time for the peripheral circuit region and the memory cell region.
Then, a well-known technique is used to perform patterning of the silicon nitride film 312. As a result, what is formed is a cap insulation film 319 that is made of the silicon nitride film 312 and which covers an upper surface of the W film 317 corresponding to a formation region of the gate electrode 335 of the planar transistor.
Then, the cap insulation film 319 is used as an etching mask, and patterning of the step-reduction Poly-Si film 334, the Poly-Si film 308, and the metal laminated film 309 by anisotropic dry etching is performed. As a result, what is formed is the gate electrode 335 that is made up of the step-reduction Poly-Si film 334, the Poly-Si film 308, and the metal laminated film 309. The gate electrode 335 is formed at the same time as the bit line 321, which is disposed in the memory cell region, is formed.
After that, a well-known technique is used to form an interlayer insulation film 337, which fills the space between the gate electrodes 335. In this manner, the peripheral circuit section 330 is formed.
The step-reduction Poly-Si film 334 is a film that is designed to offset a difference in height between the bit line 321 and the gate insulation film 333 disposed in the peripheral circuit region, which is caused by a step that is equal in thickness to the bit-contact interlayer insulation film 304 between the memory cell region and the peripheral circuit region.
The bit line 321 is made up of the Poly-Si film 308 and metal laminated film 309 that are laminated. The gate electrode 335 disposed in the peripheral circuit region is made up of the step-reduction Poly-Si film 334, Poly-Si film 308, and metal laminated film 309 that are laminated.
The problem is that the use of Poly-Si film (i.e. the Poly-Si film 308 and the step-reduction Poly-Si film 334), which is higher in resistance than metal, leads to an increased wiring resistance as the miniaturization goes on. In particular, this problem becomes conspicuous when the Poly-Si film 308 is used in the bit line 321.